TSMC's CoWoS packaging โ the bottleneck every AI chip has to pass through โ is booked solid with 52-78 week lead times in 2026, and Nvidia controls roughly 60% of that capacity versus AMD's 11%.
That's the short answer. The longer answer is that "AI chip shortage" stopped being one shortage a while ago โ it's now a stack of three separate bottlenecks (foundry wafers, CoWoS packaging, and HBM memory), and each vendor's real supply position depends on how much of each layer they've locked up. Below, I've ranked the 6 companies that actually determine how much AI compute reaches the market in 2026, based on current allocation data, lead times, and backlog figures.
Is the AI chip shortage over in 2026, or just changed shape?
The AI chip shortage is not over in 2026 for the most advanced parts โ it's shifted from raw GPU scarcity to a packaging and memory bottleneck. TSMC's CoWoS lines are fully booked 52-78 weeks out, SK Hynix's 2026 HBM output is already almost entirely allocated, and Blackwell-class B200/GB200 systems remain hyperscaler-locked and effectively unavailable outside pre-existing forward orders from Microsoft, Google, Meta, and Amazon.
It helps to separate the three layers that people lump together as "the chip shortage." First, wafer fabrication โ TSMC's leading-edge nodes, where 2nm capacity is already booked through 2028. Second, advanced packaging โ CoWoS, the process that bonds HBM stacks onto the GPU substrate, which is the layer with the tightest near-term constraint right now. Third, HBM memory itself, made by SK Hynix, Samsung, and Micron, which has its own separate wafer-start ceiling. A chip can clear the first bottleneck and still sit in queue for months waiting on the second or third โ which is exactly what's happening to Blackwell orders placed today.
AI chip supply ranked: the 6 companies that decide who gets compute in 2026
Ranked by real allocation share, backlog size, and how exposed each company is to the CoWoS and HBM constraints choking the entire category this year.
AI chip vendors compared: allocation, lead times, and backlog
| Vendor | CoWoS / capacity position | Current lead time | 2026 market share | Primary product |
|---|---|---|---|---|
| TSMC | Sole CoWoS supplier, fully booked | 52-78 weeks (packaging) | ~90% of advanced AI chip fabrication | Foundry + CoWoS-S/CoWoS-L |
| Nvidia | ~60% of CoWoS allocation | 36-52 weeks (H200/B200) | 70-81% AI accelerator revenue | H200, B200, GB200 Blackwell |
| Broadcom | ~20% via ASIC customer allocation | Not disclosed separately | ~60% custom ASIC design share (2027E) | Custom AI ASICs (TPU, Trainium partner) |
| Via Broadcom fab partnership | ~1M TPU units to Anthropic by late 2026 | Not broken out separately | TPU (Ironwood generation) | |
| Amazon | Via Broadcom/Marvell fab partnership | 500K+ Trainium2 deployed | Not broken out separately | Trainium2 |
| AMD | ~11% of CoWoS allocation | Not disclosed separately | 6-8% AI accelerator revenue | MI300/MI355X Instinct |
Figures are Q2-Q3 2026 estimates blended from Silicon Analysts foundry allocation reporting, Counterpoint Research, Tom's Hardware custom ASIC coverage, CNBC hyperscaler chip reporting, and company earnings disclosures. Several vendors do not separately break out AI-specific chip revenue from total segment revenue.
Why HBM memory is still the hidden AI chip shortage in 2026
Every AI accelerator on this list needs High Bandwidth Memory bonded onto it via CoWoS, and HBM itself is separately supply-constrained. SK Hynix executives have confirmed their 2026 HBM output is almost entirely allocated already, global HBM wafer starts sit near 350,000 against demand that significantly exceeds that figure, and TSMC's own CEO has said packaging capacity remains roughly three times short of HBM-driven demand. Samsung and Micron are both ramping HBM capacity, but neither is expected to meaningfully ease the shortage before late 2026 at the earliest.
TSMC's CoWoS expansion is targeting roughly 25% higher output by late 2026, but AI accelerator demand is growing faster than that projection, which is why lead times have kept climbing through the year rather than stabilizing. Meaningful new packaging capacity is expected online in the second half of 2026 โ the real gating factor for how much Blackwell and MI355X volume actually ships โ but most forecasters now expect the combined HBM-and-CoWoS constraint to persist into at least the first half of 2027.
What the AI chip supply ranking means for buyers and investors
For anyone actually trying to buy compute in 2026, the practical lesson from this ranking is that allocation share matters more than announced specs. AMD's MI355X is competitive on paper, but an 11% CoWoS allocation versus Nvidia's 60% means AMD simply cannot ship enough units to seriously dent Nvidia's ~70-81% AI accelerator revenue share this year, regardless of price-performance โ the constraint is structural, not commercial. That's the same dynamic reshaping the layer right above the chip itself, where AI networking vendors are also racing to reduce dependence on a single company's bundled stack.
As an investor, the more interesting story here is Broadcom's custom ASIC business, which is growing shipments 44.6% year-over-year โ nearly triple merchant GPU growth โ precisely because hyperscalers like Google, Amazon, and Meta are willing to spend years and billions of dollars building their own silicon just to get out from under CoWoS allocation queues they don't control. That's a rational response tracked closely alongside overall AI infrastructure spend on our Big Tech Earnings dashboard, and it's worth watching whether custom ASIC volume actually displaces merchant GPU share once the packaging bottleneck eventually clears.
I've made 65+ investments and the pattern here is a familiar one: when a single company controls the scarcest input in a fast-growing category โ in this case, TSMC's CoWoS lines, not any one chip design โ every other vendor's roadmap becomes a negotiation over allocation, not a pure product competition. Nvidia's 60% CoWoS share is arguably a more durable moat right now than any architectural advantage in Blackwell itself, because it can't be out-engineered โ only out-negotiated with TSMC, or routed around entirely via custom ASICs the way Google, Amazon, and Broadcom are doing.
For founders building on top of any of these chips, the practical implication is procurement risk that didn't exist two years ago: a startup locking in compute today for a model to be trained in early 2027 needs to plan around 52-78-week packaging lead times as a real constraint, not a footnote, the same way hardware startups have always had to plan around component lead times. Cloud GPU marketplaces and reserved-capacity deals with hyperscalers exist precisely to smooth over this allocation math for smaller buyers who can't negotiate directly with TSMC or place billion-dollar forward orders the way Microsoft, Google, Meta, and Amazon can.
The Bottom Line:
The AI chip shortage in 2026 isn't about GPU designs anymore โ it's about who controls TSMC's 52-78-week CoWoS packaging queue and the nearly sold-out HBM supply underneath it. Nvidia's ~60% allocation share explains its dominance better than any spec sheet, Broadcom's $73 billion ASIC backlog shows hyperscalers are willing to pay years of R&D to route around the bottleneck, and AMD's ~11% share is the real reason it can't yet close the gap on price-performance alone.
Track AI infrastructure spending on the Big Tech Earnings Dashboard and see how AI-native companies are valued on the AI Valuations Dashboard at Value Add VC. Originally published in the Trace Cohen newsletter.
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