Analysis
IBM unveiled a next-generation mainframe processor at Hot Chips 2026 whose cores can natively execute both its own z/Architecture instruction set and Arm's AArch64 instructions, switching between the two within nanoseconds, The Register reported. The chip has 11 high-performance cores built on a 2nm process, running at a 5.7 GHz base frequency, with IBM targeting availability around 2028.
The problem it actually solves
The design solves a real, specific problem rather than a theoretical one. IBM's mainframes, running z/OS, still anchor core transaction processing at most large banks, insurers and government agencies -- workloads that are too deeply embedded, too regulated, or simply too expensive to migrate off the platform. But the AI tooling ecosystem, from training frameworks to inference runtimes, has overwhelmingly standardized on Arm-native and x86 Linux environments. That gap has forced enterprises with mainframe-resident data to move data off the mainframe to run modern AI workloads against it, adding latency, cost and a data-governance headache in the process.
“But the AI tooling ecosystem, from training frameworks to inference runtimes, has overwhelmingly standardized on Arm-native and x86 Linux environments.”
A chip that runs both instruction sets natively in the same core, rather than through a separate co-processor or a virtualized partition, means Arm-native Linux applications -- including AI frameworks -- can run directly alongside z/OS transaction processing on the same physical hardware, with the same low-latency access to the data that never has to leave the machine. IBM has previously offered various forms of Linux-on-mainframe support through partitioning, but native dual-ISA execution within a single core is a materially deeper integration than prior approaches.
- IBM -- the sole vendor developing this dual-ISA design, extending its LinuxONE and Z mainframe lines
- Arm -- whose instruction set architecture IBM is natively supporting to access the broader AI and Linux software ecosystem
- Enterprise mainframe customers in banking, insurance and government -- the direct beneficiaries, given the amount of regulated, latency-sensitive data that has never left mainframe systems
The competitive context is that IBM's mainframe business, while a shrinking share of enterprise IT spend overall, remains a high-margin, deeply entrenched franchise with few credible alternatives for its specific workloads -- there is no realistic near-term migration path off z/OS for a large bank's core ledger system. A chip that makes the platform more AI-compatible extends the moat around that franchise rather than opening it to new competition. Pulse previously covered IBM's push into sub-1-nanometer chip technology, the process-node research this dual-ISA design ultimately builds on.
The practical limitation is the 2028 timeline: this is an architecture announcement at a chip conference, not a shipping product, and enterprise hardware refresh cycles on mainframes run in years, not quarters. Banks and insurers evaluating whether to wait for this generation versus deploying AI workloads through existing partition-based approaches now have a real tradeoff to make between near-term capability and a materially better long-term architecture.
IBM has not disclosed specific performance benchmarks for AI workloads running natively on the new cores versus the same workloads running through existing Linux-on-Z partitioning, and z16 and z17 predecessor announcements both slipped roughly two quarters between architecture reveal and general availability -- a pattern worth pricing into any 2028 planning that assumes this ships on schedule.
